1. Field of the Invention
This invention relates generally to the field of circuits for recovering or regenerating synchronizing signals from video signals, and in particular, to the field of digital horizontal phase locked loop circuits.
2. Description of Related Art
Phase locked loops are used in television receivers for generating a local horizontal synchronizing signal which is synchronous with the horizontal synchronizing component of an incoming video signal. Phase locked loops generally comprise a voltage controlled oscillator for regenerating the synchronizing signal, a phase detector for comparing the phase of the regenerated synchronizing signal with an input signal and generating an error or correction signal, and a low pass filter for developing a control voltage for the oscillator. Phase detectors and oscillators in digital phase locked loops can be implemented by clock driven counters. The filter can be implemented by combinations of latches, accumulators, summing circuits and multipliers. The precision of a digital phase locked loop depends in part upon the resolution of the digital calculations in measuring the phase errors and in controlling the frequency of the oscillator. The resolution in turn is a function of the clock frequency driving the counters and the capacity, if any, of the digital circuitry to perform calculations representative of fractions of the clock period. Generally speaking, the complexity of a digital phase locked loop is a function of the accuracy required in regenerating the synchronizing signal.
Certain applications require high clock frequencies and accuracy within fractions of the clock period. This minimizes jitter due to the higher resolution, in timing or phase, employed for tracking the incoming signal. Other applications may require less accuracy, although minimizing jitter remains an important design criteria. In certain kinds of video displays, for example picture-in-picture, it may not be practical to utilize all of the video information available for the auxiliary or smaller inset picture. There can be too much video information to fit in the smaller area available. In these circumstances, the video information is subsampled. Only one sixteenth of the video information, for example, may be utilized. This means that fewer horizontal lines are utilized and that less information on each line is utilized. The display of such subsampled information can tolerate less accuracy in the regeneration of the horizontal synchronizing signal, and in accordance with an inventive arrangement, a less complex digital synchronizing circuit can be implemented for this circumstance. Even so, jitter must be minimized.
Synchronizing circuits can reconstruct or recover synchronizing signals by generating two time intervals which correspond to two partial periods or pulse parts of a signal. The two partial periods or pulse parts can be combined to form the regenerated signal. Many digital synchronizing systems adjust the duration of each time interval, and consequently each partial period or pulse part, in order to achieve maximum accuracy. This technique requires that two time intervals or partial periods be adjusted responsive to each phase measurement for each period of the reconstructed signal, and consequently, circuitry for processing the phase measurement and adjusting the counter or counters used to implement the oscillator.
A signal which can be very convenient for supplying the clock rate is based on the color subcarrier frequency f.sub.SC, and in particular, has a frequency of 4.times.f.sub.SC. A time interval of 910 clock pulse periods at 4.times.f.sub.SC, which is approximately 14.3 MHz, corresponds to the nominal period of the horizontal synchronizing component of a conventional video signal in an NTSC system.